1. Field of the Invention
The invention relates to verification of layouts used in fabrication of semiconductor wafers that contain integrated circuits (ICs). More specifically, the invention relates to a method and an apparatus for evaluation of criteria related to critical dimension (CD), such as conformity to user specification(s) of CD and/or uniformity of linewidth.
2. Related Art
In the manufacture of integrated circuit (IC) chips, minimum feature sizes have been shrinking according to Moore's law. Currently the minimum feature size is smaller than the wavelength of light used in the optical imaging system. Accordingly it has become increasingly difficult to achieve reasonable fidelity (including resolution and depth of focus) between (a) a layout as designed in a prior art computer in a place and route step 101 (FIG. 1A) and (b) shapes of circuit elements formed in a wafer fabrication step 106 (FIG. 1A). Step 106 normally involves a number of processes such as photolithography followed by metal deposition and chemical mechanical polishing. A result of place and route step 101 is a layout of rectangles shown in FIG. 1B. This illustrative layout has four traces (also called “lines”) whose nominal contours (i.e. as designed in the computer) are shown by dashed rectangles 111n-114n. Also shown in FIG. 1B are closed contours 111i-114i which denote shapes of corresponding metal (or other material) as they would be formed if a wafer is fabricated using the layout.
In today's design flows, it is common to perform, after a tapeout step 104, a step 105 (called “mask synthesis”) involving optical proximity correction and resolution enhancement, followed by a step 105a of physical verification. In step 105a, a simulation is performed of a lithographic process to be used to build the integrated circuits in a semiconductor wafer, and the simulation generates image intensities to which are applied one or more evaluation criteria such as measurement of critical dimension of contours (such as contours 111i-114i in FIG. 1B). Note that if step 105a finds errors, then the design flow may return to step 105 for additional RET or OPC based corrections but if such changes are insufficient to fix the errors, the flow may return to step 102 (as shown by the dashed arrow in FIG. 1A).
A human user of the prior art computer is typically interested in the minimum width of each trace (also called “critical dimension” and abbreviated as CD) for several reasons, e.g. when CD is too small an IC in the wafer may not perform as designed. In FIG. 1B, the minimum width 113wmin of trace 113 illustrates such a CD. The user may also be interested in uniformity of a trace's width along a longitudinal direction. In FIG. 1B, trace 113i has a maximum width 113wmax larger than nominal width 113w, which can cause a problem.
Determination of dimensions 113wmax and 113wmin can be performed as follows, using a method known to the inventors as follows. A nominal rectangle 113n that represents a to-be-formed trace in the IC is divided up into a number of rectangular portions, such as portions 120, 130 and 140 illustrated in FIG. 1C. Note that all portions of nominal rectangle 113n are not labeled in FIG. 1C, but these portions together appear like a track of a train (hence the method is also called a “gauge” method, and the portions are also called “gauge” portions).
Thereafter, the following process (called “bisection”) is repeated for each gauge portion of nominal rectangle 113n. A prior art aerial image simulator is invoked to find (1) a first intensity (FIG. 1D) at nominal center 121 of a current gauge portion, (2) a second intensity a location 122 outside a nominal edge 125 of the current gauge portion, and (3) a third intensity at a midpoint 123 between the location 121 of the first intensity and the location 122 of the second intensity. Note that all the just-described locations 121, 122, 123 and 125 are located at an edge of a gauge portion (e.g. left vertical edge of gauge portion 120 in FIG. 1C) that is transverse to the feature (the feature's nominal polygon 113n is a rectangle that is shown horizontally oriented in FIG. 1C). Then, the third intensity is compared with a known threshold (which when applied to an intensity distribution of the lithographic process, results in a contour).
If the currently-computed third intensity is less than threshold, then its location 123 is used in a next iteration to invoke the aerial image simulator to re-compute the second intensity, followed by re-computing the third intensity again. If the currently-computed third intensity is greater than threshold, then its location 123 is used in the next iteration to invoke the aerial image simulator to re-compute the first intensity, followed by re-computing the third intensity (this time at location 124 in FIG. 1C). In this manner, a number of iterations are performed until a terminating criterion is met. The terminating criterion for the bisection process may be, for example, that the locations of the first and second intensities are sufficiently close to one another (e.g. locations 123 and 124 are sufficiently close) that they fall below a user-specified tolerance on CD location. When such a criterion is met, a linear interpolation between these two locations is used to find the position of contour 113i in the current gauge portion. After such contour positions are determined in every portion, the smallest width among all gauge portions forms the CD.
A prior art aerial image simulator that is used in such a method typically applies a number of mathematical formulations to layout shapes to simulate the lithography process, including not only optical effects (such as resolution and depth of focus) but also resist effects, etch effects etc. A combination of such effects in a semiconductor wafer fabrication process is used to create a layer in the wafer, for example, a metal layer or a polysilicon layer. A prior art aerial simulator may use a kernel-based model of the wafer fabrication process, by convolving an IC layout with convolution kernels to obtain the intensity at a location in a simulated wafer image.
One problem with the bisection process described above is that the aerial image simulator (used to simulate the lithography process) is invoked multiple times in each iteration. Accordingly, determining the location of edges of a single portion in the can easily require several invocations of the aerial image simulator (e.g. 10 invocations), and if there are several portions (e.g. 10 portions), then the total number of invocations per trace is quite large (e.g. 100 invocations total). Inventors find that when an aerial simulator is used so many times, the gauge method be easily scaled up for use in evaluating an IC layout in a reasonable amount of time (a few hours), given the current state of typically-used computing resources (e.g. a workstation containing a 2 GHz CPU and 1 GB memory).
U.S. patent application Ser. No. 11/142,789 entitled “CENTERLINE-BASED PINCH/BRIDGE DETECTION” filed on May 31, 2005 by ZongWu Tang, Juhwan Kim, Daniel Zhang, Haiqing Wei and Gang Huang is incorporated by reference herein in its entirety as background to the current invention. This patent application describes performing lithography simulation only along a centerline of a feature in an IC layout. The layout features whose centerlines are selected (for invoking an aerial image simulator) can either be layout elements, or spaces between layout elements. Certain embodiments simulate the lithographic process only along center lines of features selected for being likely to generate defects in lithography (e.g. a long and narrow layout element that is closely surrounded by other layout elements or a space between layout elements with long facing edges). However, the just-described centerline method can result in some errors under certain circumstances, e.g. (1) if intensity peak has drifted from nominal center of the trace (due to proximity effect of adjacent traces) or (2) if a corner is present adjacent at the end of the trace.
Accordingly, the inventors find there is a need for yet another method to evaluate criteria related to critical dimensions of an IC layout that is faster than the gauge method, and not prone to errors of the centerline method.